1. Field of the Invention
The disclosed invention relates generally to fabrication of integrated circuits, and more particularly, but not by way of limitation, to wiring levels on an integrated circuit in a back-end-of-line (BEOL) processing that include active and/or nonlinear devices embedded therein.
2. Description of the Related Art
From the beginning of semiconductor manufacture, there has been a progressive trend to miniaturizing electrical components through dimension scaling, thereby resulting in increased circuit density over time. In the general manufacturing scheme of an integrated circuit (IC), there are two major parts, the front end of line (FEOL) processing and the back end of line (BEOL) processing.
In general, the FEOL layer contains active and nonlinear devices requiring a semiconductor, such as transistors, diodes, varactors, photodetectors, photo-emitters, polysilicon resistors, MOS (metal-oxide-silicon or metal-oxide-semiconductor) capacitors, waveguides, waveguide modulators, etc. The BEOL contains passive, linear devices made from metals and insulators, such as signal and power wires, transmission lines, metal resistors, metal-insulator-metal (MIM) capacitors, inductors, fuses, etc. The FEOL processing may include a transistor and other active or nonlinear devices being formed on a semiconducting wafer surface, for example a Si wafer, and the back end of line (BEOL) may include the devices being wired together with a patterned multilevel metallization processes.
To support the increased component density, a hierarchical wiring method was developed for the BEOL, in which multiple levels of interconnect wires are fabricated in a level-by-level scheme. The BEOL then generally includes a plurality of wiring levels to provide interconnections for the FEOL devices to carry the signals therebetween. A set of far BEOL (FBEOL) connections is formed, and the integrated circuit (IC) is then finally protected by a sealing layer. Completed IC's are tested, including a plurality of electrical tests to determine a proportion of the devices on the wafer that perform within certain preset parameters to provide a yield.
To fabricate the BEOL interconnect layers, a damascene or dual damascene process is commonly used and is known in the art. The dual damascene process allows for hierarchical wiring management and reduced cost.
As dimension scaling reaches fundamental limits, one general approach to increase the IC density and functionality has been to combine two prefabricated IC's in a stacked or three dimensional (3-D or 3D) IC. This is a high cost solution. For example, wafer bumping is one 3D packaging technology, in which two or more layers of active electronic components are integrated into a single 3D circuit or package. Currently, a 3D integrated (IC) chip requires that more than one IC layer be fabricated independently (be it partial or full fabrication), stacked, and then packaged together. The yield in the latter steps is low, again leading to increased cost. Therefore, a new method is needed to help in the wiring of the devices in order to help increase the circuit density and still provide a high yield and reduced cost.
The prefabrication of more than one integrated circuit (IC) also requires that more than one silicon wafer be used. A separate substrate is necessary for each prefabricated device layer that is bonded together. Moreover, there are many extra steps and inherent problems of the subsequent stacking and bonding of the ICs, and these steps lead to increased cost of the stacked 3-D IC. In one example, two IC chips can be bonded together with the aid of insulating and adhesive layers in order to stack two IC chips together. The bonding can be made by thermo-compression, fusion bonding, oxide bonding, or by use of an intermediate bonding layer, for example, an adhesive.
Generally, a bonded structure can include a semiconductor device layer stack and a first set of functional elements, such as BEOL interconnect elements. The BEOL interconnect elements can at least partially connect the circuits present in the semiconductor device layer. The stacked components are separately formed, and then bonded after being stacked. However, in order to implement a 3D stacked IC solution, reliability and high yields of individual elements along with very high bonding yields and precise alignment methods need to be realized.
There have been a plurality of other problems in the bonding process including having to deal with the forces that are required to form a strong wafer bond. For example, higher forces acting on a mechanically weak BEOL structure may damage that structure. Then, the prefabricated device layers must be modeled and modified in design in order to take account of the inherent forces due to deformation during bonding and subsequent cool down.
Additionally, there are problems with the bonded contacts. These include reliability over use, defects, and degradation of circuit performance. There are also problems in that extra steps are necessary for the fabrication process at the back-end in order to have more than one active layer. This can increase costs and increase the possible defects of the final product.
Therefore, there is also a need to improve the overall mechanical strength of the BEOL hierarchical wiring structures.
Moreover, there is a problem in reduced yield as the circuit density has increased. Additionally, the performance of signals traveling through interconnects has degraded with the increased wiring density. The BEOL interconnects have become mechanically weaker with the use of low-k and porous dielectrics to regain signal performance.
There is a need for increased density and high perfoiniance in the integrated circuits such that circuit function can be distributed amongst a plurality of circuit layers without adversely impacting circuit performance and increasing manufacturing costs.
Therefore, it is also desirable to provide improved BEOL structures incorporating individual devices interconnected with wiring on the wafer that allows for increased circuit density as compared to present day chips while still increasing performance and yield.